Raspberry Pi – RP2350 MCU – Revision A4 Released!

Raspberry Pi – RP2350 MCU & RP2354 SiP: With the RP2040 microcontroller, Raspberry Pi started to offer ICs developed in-house. The developers from Cambridge continued this with the RP1, a PCIe interface bridge that is used on the Raspberry Pi 5.

The new MCU RP2350 was introduced in 2024 and is now available in the A4 revision. In this new hardware revision, Raspberry Pi has fixed some errata discovered together with the community. Overall, the RP2350 is a significant upgrade to the RP2040 in many features.

The dual-core idea was continued in the RP2350 and the RP2354A/B SiP derivatives are the first controllers with integrated flash from Raspberry Pi to be available. For a quick start or easy integration into your application, the Raspberry Pi Pico 2 boards are available in the proven form factor.

RP2350 – More Performance and Features

Raspberry Pi has not only integrated 2 ARM Cortex-M33 cores in the RP2350, but also 2 additional RISC-V Hazard3 cores. The main clock is specified up to 150MHz. However, the RP2350 is a dual-core MCU, so only 2 cores can be active. The selection can be determined by software or by on-chip OTP memory.

The RP2350 has 520kB SRAM, but no integrated flash. This or a PSRAM can be connected via the XIP unit using the QSPI interface.

The universal PIO, already introduced with the RP2040, has been made even more efficient and powerful. Since the use of the PIO is a complex topic, Raspberry Pi has dedicated a separate chapter to this flexible peripheral in the Raspberry Pi Pico-series C/C++ SDK document, which goes far beyond the standard interface implementation (UART, I2C, PWM, SPI, …) in the datasheet. This allows developers to be very creative when implementing interfaces with the PIO.

SecureBoot (verification of binaries via signature check) and Encrypted Boot (the OTP in the RP2350 contains the keys for decrypting binaries when loading them into the SRAM). The ARMv8 architecture of the Cortex-M33 features SAU & MPU regions that enable the separation of secure and non-secure code.

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