Implementing advanced motor control often requires a robust solution that offers the performance of a Digital Signal Processor (DSP) engine and the versatile peripherals of a microcontroller. Our dsPIC® Digital Signal Controllers (DSCs) offer key features and specialized peripherals to meet a variety of requirements for high-performance applications.
These applications require safe and reliable operation to protect end-user well-being. Most of the time, electrical systems operate as intended, but in the event of unexpected condition or system malfunction, safety specifications such as ISO 26262, IEC 60730 and IEC 61508 are used to ensure that manufacturers have designed their products to operate safely.
For example, our sensorless Field Oriented Control (FOC) algorithm makes use of a single-cycle MAC with data saturation, zero overhead looping and barrel shifting for exceptional performance. Discover how dsPIC DSCs, along with our ecosystem of development tools, software and other design resources, make it easy to develop your next Brushless DC (BLDC) motor, stepper motor, Permanent Magnet Synchronous Motor (PMSM) or AC Induction Motor (ACIM) application.
Select dsPIC33 DSCs have been designated as “Functional Safety Ready.” A product that contains the “Functional Safety Ready” designation offers integrated hardware safety features, Failure Modes, Effects, and Diagnostic Analysis (FMEDA) reports, safety manuals, and, in some cases, diagnostic software libraries. A TÜV SUD-certified C-compiler and a complete and fully qualified development environment are also available.
Functional |
ISO 26262 |
IEC 61508 |
IEC 60730 |
|
Hardware Safety Features |
||||
Safety Library |
ASIL B and ASIL C Compliant |
Releasing Soon |
||
AUTOSAR® MCAL Drivers |
Yes* |
N/A |
N/A |
|
Safety Manual |
Yes* |
Releasing Soon |
N/A |
|
FMEDA Reports |
Yes* |
Releasing Soon |
N/A |
|
TÜV SUD-Certified Compiler |
||||
Code Coverage Tools |
MPLAB Code Coverage or third-party tools from vendors such as LDRA |
Product Family |
CPU |
CPU Speed |
Program Memory |
AEC Q100 |
Applications |
Dual Core |
90 + 100 MIPS |
Up to 512 KB |
Grade 0 |
High-Performance Embedded |
|
Single Core |
100 MIPS |
Up to 256 KB |
Grade 0 |
High-Performance Embedded |
|
Single Core |
70 MIPS |
Up to 128 KB |
Grade 1 |
High-Performance Embedded |
|
Single Core |
70 MIPS |
Up to 256 KB |
Grade 0 |
High-Performance Embedded |
Dedicated peripherals and functions have been integrated into PIC24 and dsPIC33 devices to help increase the reliability and monitoring for safety-critical applications. These features help ensure that end applications operate as intended, with safe shut down if any exception or issue arises.
Feature |
dsPIC33C |
dsPIC33E |
PIC24F |
Fault Prevention |
Self Diagnostic |
System Diagnostic |
Fault Mitigation |
CRC Module/Cyclical Redundancy Check (CRC)* |
● |
● |
● |
|
✔ |
✔ |
|
Flash Error Detection and Correction (ECC) |
● |
○ |
○ |
|
✔ |
|
✔ |
Read/Write Memory Protection |
● |
● |
● |
✔ |
|
|
|
Boot Segment Protection |
● |
● |
○ |
✔ |
|
|
|
Dual Partition Program Memory |
● |
○ |
○ |
✔ |
✔ |
|
|
Illegal Opcode Detect |
● |
● |
● |
|
✔ |
|
✔ |
Load Once Per Reset Config Register |
● |
● |
● |
|
|
|
✔ |
RAM BIST |
○ |
– |
– |
|
✔ |
|
|
Self-Readable Flash Memory |
● |
● |
● |
|
✔ |
Vienna 3-Phase Power Factor Correction (PFC) Reference Design
The MSCSICPFC/REF5 is a 3-phase Vienna PFC reference design for Hybrid Electric Vehicle/Electric Vehicle (HEV/EV) charger and high-power switch mode power supply applications. This reference design achieves 98.6% efficiency at 30 kW output power.